1. Field of the Invention
This invention relates generally to the structure and fabrication process of trenched DMOS power transistors. More particularly, this invention relates to a novel and improved structure and process for fabricating a trenched DMOS power transistors provided with specially trenched channel stop structure in the termination areas to prevent leakage current by terminating a depletion current channel with a drain voltage applied over a thin oxide layer lining the specially configured trenched channel stops.
2. Description of the Prior Art
Leakage currents in the termination areas caused by an ineffective channel stop is still a technical difficulty faced by the designers and manufacturers of the trench semiconductor power devices. This difficulty is due to the special structural features in the termination areas of the trenched double-diffusion metal oxide semiconductor (DMOS) transistors. The structure differences in termination areas between the planar and trenched DMOS lead to the channel stop which is typically implemented and function properly in a planar transistor, to fail in carrying out the channel stop functions for a trenched double-diffusion metal oxide semiconductor (DMOS) device. As a result of this ineffective channel stop for the trenched transistors in the termination areas, leakage currents are often experienced which leads to degradation in device performances. In order to terminate this leakage current, some devices are manufactured with additional mask to form a specially configured channel stop in the termination area. Production costs are increased due to additional processing steps involved in applying an extra mask in a trenched semiconductor power device for the purpose for stopping the leak current.
In order to better understand the technical background of the present invention, the channel stops typically implemented for a planar device is first described. FIG. 1A is a cross-sectional view of a p-channel planar DMOS transistor 10 near the termination area. The DMOS transistor 10 is supported on a P+ substrate 15 and an P- epi-taxial layer 20 formed on its top. The transistor 10 includes a n-body region 25 with a heavily doped n+ body contact region 30 in electrical contact with a body contact 40. The transistor 10 further has a field oxide 35 defining the termination area where a channel stop 45 is formed. In order to properly configure the channel stop 45 in the termination area outside of the field oxide 35, before the termination n-body region 25' and the source region 28 are insulated by a PSG or BPSG protection layer 38, a channel stop poly 44 is formed with a thin oxide layer 50 underneath. By adding a channel stop poly 44 which is electrical contact with the source 28 through the metal layer of channel stop 45. The channel stop poly 44 has a voltage equivalent to the voltage of the epi region 20 and the drain region 15 since the termination body region 25' is floating. The drain voltage in the channel stop poly 44 is applied through the thin oxide layer 50 to stop a channel, formed by the depletion layer, as that shown by the dotted lines for conducting electrical current. Thus a leakage current in the termination area is stopped by applying a drain voltage through a thin oxide layer 50 to an immediate under-layer to cut off a current flow by forming a channel stop poly layer 44 connected to the termination source region 28 while coupled to the depleted channel layer immediately underneath the thin oxide layer 50 below the poly layer 44.
FIG. 1B is a cross sectional view of a trenched DMOS transistor 60 including the core cell area and the termination area. The core cell area includes a plurality of trenched DMOS cell with the poly gate formed in the trenches. For the sake of simplicity, since these cells are standard cells, no detail description would be necessary for illustrating the technical difficulties of the channel stop for the trenched DMOS. In the termination area which is shown on the right hand side of the field oxide 65, a protective BSG or BPSG layer 70 is formed thereon. A channel stop 75 is formed with a metallic layer, e.g., an aluminum layer, overlying a body contact region 80 in a n-body region 85. As shown by the dotted lines for a current channel formed in the epi-region 90 supported by the substrate 95, the channel for current flow cannot be stopped by the channel stop 75. The channel stop has a drain voltage. However, the drain voltage in the channel stop 75 cannot be effectively applied to the underneath layer near the channel region 98 due a greater thickness of the oxide field 70. A leakage current is conducted to flow through the depleted channel region 98 to a recombination zone 99 in the edge of the termination area for charge recombination thus forming an undesirable leakage current in the termination area.
For those of ordinary skill in the art, a device structure in the termination area as that shown in the cross sectional view of FIG. 1B is most commonly implemented. This structural difference is produced by employing a manufacture process-flow which is commonly applied as will be described below illustrated with FIG. 2. Unlike a planar device, the polysilicon for the trenched transistors is now deposited into the trenches. The polysilicon layer which is formed above the trench is then removed by a planarization process including the poly layer above the trenches in the termination areas. Therefore, in contrast to a planar DMOS, the polysilicon layer with a thin oxide layer is removed for a trenched DMOS device in the area underneath the channel stop 75. The channel stop 75 is not in contact with a polysilicon layer with a thin oxide layer underneath. Instead the channel stop 75 is insulated by a field oxide layer 65 of much greater thickness. Due to this structural difference, the channel stop which generally function properly for a planar device is not effective when the poly layer with the thin oxide layer underneath are removed during a standard trenched DMOS planarization process.
A processing flow commonly employed to manufacture the trenched DMOS transistor 60 is illustrated in FIGS. 2A to 2E. As shown in FIG. 2A, the processing steps begins by first growing a P epitaxial layer on top of a P.sup.+ substrate 95. An initial oxidation process is performed to grow an oxide layer 65 and active mask is employed to remove a portion of the initial oxide layer 65 to define the active regions. A blank n-body implant is carried out with phosphorous ions to form the n-body region 85. A n-body diffusion process is then carried out at an elevated temperature to increase the depth of the n-body region 85. A photo-resist is applied as the trench mask 84.
Referring to FIG. 2B. with photoresist 84 employed as a trench mask, a trench etch process, which is a dry anisotropic etch process, is carried out to form trenches. A sacrification oxidation process is to form oxide layer which is followed by a sacrification oxide etch process. A gate oxide layer 86 is then formed by a gate oxidation process. A poly deposition process is performed to deposit a poly layer 88. Referring to FIG. 2B, a planarization etch is performed to form a planar surface by etching a top layer to 0.2-0.5 .mu. from the deposited poly. A P+ implantation process is carried out to dope the poly layer 88. A poly etch is carried out to dry etch the poly layer 88 till the top surface is removed with the end-point detection to terminate the etch process when the polysilicon layer above the trench is removed.
Referring to FIG. 2C, a P+ block mask 89 is applied to carry out an P+ implant to form the P+ region 91. The P+ implantation is carried out with a boron ion beam, then the resist, i.e., the P+ blocking mask 89, is stripped. Referring to FIG. 2D, the P+ source regions 91 are driven into desired junction depth by a diffusion process. A BPSG or PSG is deposited to form an insulation layer 70. A BPSG flow or BSG densification process is performed. Referring to FIG. 2D, a contact mask (not shown) is applied to perform an etch process to define the contacts windows in order to be ready for making source and gate contacts. A blank phosphorous implant is carried out to form the n+ regions 93 for providing a low-resistance body contact of the DMOS cell. A metal deposition process is carried out to form an overlaying metal layer. The final DMOS transistor is completed by applying a metal mask to pattern the source contact, the gate contact, the field plate and the channel stop (CS). By the use of this standard process flow, the channel stop 75 in the termination area is formed which is insulated by a field oxide layer 65 as that shown in FIGS. 1B and 2E. The channel stop 75 is not effective to prevent a leakage current flowing through a depletion channel layer 98.
In order to overcome this difficulty, an alternate manufacture process has to be applied as that shown in FIGS. 2F to 2I. An extra mask 82 especially configured for manufacturing DMOS device with a better channel stop 75' has to be applied. This extra mask 82 is employed to block the n-body implantation into the channel strop region. The manufacture processes illustrated in FIGS. 2F to 2I are basically self explanatory. Referring to FIG. 2I the DMOS device manufactured by the use of this extra mask 82 has an improved channel stop 75' because a p-doped region 97 is now in direct contact with the channel stop 75', The leakage current flowing through a depletion region underneath the p-doped region 97 is effectively stopped with a drain voltage applied to the channel stop 75', However, the production costs are increased and more processing steps are required when this extra channel stop mask 82 has to employed.
Therefore, there a need still exits in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties. It is preferable that the improved DMOS device is manufactured with effective channel stop without requiring additional masks or more processing steps such that the production cost would not be increased for manufacturing this improved DMOS device.